Research topic and goals
The end of transistor scaling encourages us to challenge innovative architectural approaches for the future of computing. Reconfigurable architectures, such as field-programmable gate arrays (FPGA) and coarse-grained reconfigurable architecture (CGRA), offer significant potential for architectural exploration. Many emerging AI accelerators (e.g., Cerebras and Groq) are built on reconfigurability and dataflow design principles, often combining significantly distributed on-chip memories, high-speed interconnects, and domain-specific languages. In this project, we will evaluate existing reconfigurable architectures and explore hardware designs to accelerate our target workloads, which include numerical algorithms, streaming data compression, and real-time AI at the edge. We will also investigate architecture designs, design workflow (design, verification, layout, etc.), compiler technologies, architecture emulation/simulation, and emerging technologies such as Chiplet, structured ASICs, and FPGA/CGRA generators. We aim to demonstrate enhanced computing efficiency of selected workloads on reconfigurable architectures and highlight the potential of custom hardware designs even for extensive distributed resources.
Results for 2023/2024
- organized a break-out session at the JLESC 15th workshop in France and a workshop at the HEART symposium in Japan.
- published two co-authored papers at workshops held with SC23. We released the source code associated with the SC23 DRBSD paper.
Visits and meetings
- Kazutomo Yoshii (ANL) visited RIKEN for two days in June 2023 to discuss the streaming hardware compressor design.
- Juan Miguel de Haro (BSC) visited RIKEN as an intern in 2023 to port the OmpSs@FPGA infrastructure to ESSPER.
- Carlos Alvarez (BSC) visited RIKEN in June 2023 to discuss porting the OmpSs@FPGA infrastructure to ESSPER.
- Tomohiro Ueno (R-CCS) visited ANL in May 2023 to discuss hardware compressors and accelerator designs.
Impact and publications
- A paper at Smokey Mountain Conference 2021 on hardware co-design methodology (Yoshii et al. 2021)
- A paper at IEEE ASAP 2021 on virtualization of networks of FPGA clusters (Ueno, Koshiba, and Sano 2021)
- A paper at SC23 PMBS workshop (Yoshii et al. 2023)
- A paper at SC23 DRBS workshop (Yoshii et al. 2023)
- Yoshii, Kazutomo, John Tramm, Bryce Allen, Tomohiro Ueno, Kentaro Sano, Andrew Siegel, and Pete Beckman. 2023. “Hardware Specialization: Estimating Monte Carlo Cross-Section Lookup Kernel Performance and Area.” In Proceedings of the SC’23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis, 1274–78.
@inproceedings{yoshii2023hardware, title = {Hardware specialization: Estimating Monte Carlo cross-section lookup kernel performance and area}, author = {Yoshii, Kazutomo and Tramm, John and Allen, Bryce and Ueno, Tomohiro and Sano, Kentaro and Siegel, Andrew and Beckman, Pete}, booktitle = {Proceedings of the SC'23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis}, pages = {1274--1278}, year = {2023} } - Yoshii, Kazutomo, Tomohiro Ueno, Kentaro Sano, Antonino Miceli, and Franck Cappello. 2023. “Streaming Hardware Compressor Generator Framework.” In Proceedings of the SC’23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis, 289–97.
@inproceedings{yoshii2023streaming, title = {Streaming Hardware Compressor Generator Framework}, author = {Yoshii, Kazutomo and Ueno, Tomohiro and Sano, Kentaro and Miceli, Antonino and Cappello, Franck}, booktitle = {Proceedings of the SC'23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis}, pages = {289--297}, year = {2023} } - Yoshii, Kazutomo, Rajesh Sankaran, Sebastian Strempfer, Maksim Levental, Mike Hammer, and Antonino Miceli. 2021. “A Hardware Co-Design Workflow for Scientific Instruments at the Edge.”
@misc{yoshii2021hardware, title = {A Hardware Co-design Workflow for Scientific Instruments at the Edge}, author = {Yoshii, Kazutomo and Sankaran, Rajesh and Strempfer, Sebastian and Levental, Maksim and Hammer, Mike and Miceli, Antonino}, year = {2021}, eprint = {2111.01380}, archiveprefix = {arXiv}, primaryclass = {physics.ins-det} } - Ueno, Tomohiro, Atsushi Koshiba, and Kentaro Sano. 2021. “Virtual Circuit-Switching Network with Flexible Topology for High-Performance FPGA Cluster.” In 2021 IEEE 32nd International Conference on Application-Specific Systems, Architectures and Processors (ASAP), 41–48. IEEE.
@inproceedings{ueno2021virtual, title = {Virtual Circuit-Switching Network with Flexible Topology for High-Performance FPGA Cluster}, author = {Ueno, Tomohiro and Koshiba, Atsushi and Sano, Kentaro}, booktitle = {2021 IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP)}, pages = {41--48}, year = {2021}, organization = {IEEE} }
Future plans
We evaluate existing reconfigurable architectures and explore hardware designs to accelerate our target workloads. These include numerical algorithms, streaming data compression, and real-time AI at the edge. We will also investigate various architecture designs, the design workflow (including design, verification, layout, etc.), compiler technologies, architecture emulation/simulation, and emerging technologies such as Chiplets, structured ASICs, and FPGA/CGRA generators. Our goal is to demonstrate the enhanced computing efficiency of selected workloads on reconfigurable architectures and highlight the potential of custom hardware designs, even for extensive distributed resources.